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features ? core ? arm ? cortex ? -m3 revision 2.0 running at up to 48 mhz ?thumb ? -2 instruction ? 24-bit systick counter ? nested vector interrupt controller ? pin-to-pin compatible with sam7s legacy products (48- and 64-pin versions) and sam3s (48-, 64- and 100-pin versions) ? memories ? from 16 to 256 kbytes embedded flash, 128-bit wide access, memory accelerator, single plane ? from 4 to 24 kbytes embedded sram ? 16 kbytes rom with embedded bootload er routines (uart) and iap routines ? system ? embedded voltage regulator for single supply operation ? power-on-reset (por), brown-out det ector (bod) and watchdog for safe operation ? quartz or ceramic resonator oscillators: 3 to 20 mhz main power with failure detection and optional low power 32.768 khz for rtc or device clock ? high precision 8/12 mhz factory trimmed inte rnal rc oscillator with 4 mhz default frequency for device startup. in-appli cation trimming access for frequency adjustment ? slow clock internal rc o scillator as permanent low-power mode device clock ? one pll up to 130 mhz for device clock ? up to 10 peripheral dma (pdc) channels ? low power modes ? sleep and backup modes, down to 3 a in backup mode ? ultra low power rtc ? peripherals ? up to 2 usarts with rs-485 and spi mode support. one usart (usart0) has iso7816, irda? and pdc support in addition ? two 2-wire uarts ? 2 two wire interface (i2c compatible), 1 spi ? up to 6 three-channel 16-bit timer/coun ter with capture, waveform, compare and pwm mode. quadrature decoder logic and 2-bit gray up/down counter for stepper motor ? 4-channel 16-bit pwm ? 32-bit real-time timer and rtc wi th calendar and alarm features ? up to 16 channels, 384 ksps 10-bit adc ? one 500 ksps 10-bit dac ? i/o ? up to 79 i/o lines with external interrup t capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination ? three 32-bit parallel input/output controllers ? packages ? 100-lead lqfp, 14 x 14 mm, pitch 0.5 mm/ 100-ball tfbga, 9 x 9 mm, pitch 0.8 mm ? 64-lead lqfp, 10 x 10 mm, pitch 0. 5 mm/64-pad qfn 9x9 mm, pitch 0.5 mm ? 48-lead lqfp, 7 x 7 mm, pitch 0. 5 mm/48-pad qfn 7x7 mm, pitch 0.5 mm at91sam arm-based flash mcu sam3n series summary 11011bs?atarm?22-feb-12
2 11011bs?atarm?22-feb-12 sam3n summary 1. sam3n description atmel's sam3n series is a member of a family of flash microcontrollers based on the high per- formance 32-bit arm cortex-m3 risc processor. it operates at a maximum speed of 48 mhz and features up to 256 kbytes of flash and up to 24 kbytes of sram. the peripheral set includes 2x usarts, 2x uarts, 2x twis, 3x spi, as well as 1 pwm timer, 6x general purpose 16-bit timers, an rtc, a 10-bit adc and a 10-bit dac. the sam3n series is ready for capacitive touch thanks to the qtouch library, offering an easy way to implement buttons, wheels and sliders. the sam3n device is an entry-level general purpose microcontroller. that makes the sam3n the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers. it operates from 1.62v to 3.6v and is avail able in 48-pin, 64-pin and 100-pin qfp, 48-pin and 64-pin qfn, and 100-pin bga packages. the sam3n series is the ideal migration path from the sam3s for applications that require a reduced bom cost. the sam3n series is pin-to-pin compatible with the sam3s series. its aggressive price point and high level of integration pushes its scope of use far into cost-sensi- tive, high-volume applications.
3 11011bs?atarm?22-feb-12 sam3n summary 1.1 configuration summary the sam3n4/2/1/0/00 differ in memory size, package and features list. table 1-1 summarizes the configurations of the 9 devices. notes: 1. only two tc channels are accessible through the pio. 2. only three tc channels are accessible through the pio. table 1-1. configuration summary device flash sram package number of pios adc timer pdc channels usart dac sam3n4a 256 kbytes 24 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81_ sam3n4b 256 kbytes 24 kbytes lqfp64 qfn64 47 10 channels 6 (2) 10 2 1 sam3n4c 256 kbytes 24 kbytes lqfp100 bga100 79 16 channels 6 10 2 1 sam3n2a 128 kbytes 16 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81 _ sam3n2b 128 kbytes 16 kbytes lqfp64 qfn64 47 10 channels 6( (2) 10 2 1 sam3n2c 128 kbytes 16 kbytes lqfp100 bga100 79 16 channels 6 10 2 1 sam3n1a 64 kbytes 8 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81 _ sam3n1b 64 kbytes 8 kbytes lqfp64 qfn64 47 10 channels 6 (2) 10 2 1 sam3n1c 64 kbytes 8 kbytes lqfp100 bga100 79 16 channels 6 10 2 1 sam3n0a 32 kbytes 8 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81 _ sam3n0b 32 kbytes 8 kbytes lqfp64 qfn64 47 10 channels 6 (2) 10 2 1 sam3n0c 32 kbytes 8 kbytes lqfp100 bga100 79 16 channels 6 10 2 1 sam3n00a 16 kbytes 4 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81 _ sam3n00b 16 kbytes 4 kbytes lqfp64 qfn64 47 10 channels 6 (2) 10 2 1
4 11011bs?atarm?22-feb-12 sam3n summary 2. sam3n block diagram figure 2-1. sam3n 100-pin version block diagram t s t pck0-pck2 s y s tem controller xin nr s t pmc xout o s c 3 2k xin 3 2 xout 3 2 s upc r s tc o s c 3 -20 mhz pioa piob por rtc rtt rc 3 2k rc o s c 12/ 8 /4 mhz era s e tdi tdo/trace s wo tm s / s wdio tck/ s wclk jtag s el i/d s vddi n vddout tc[0..2] tclk[0:2] twck0 twd0 twck1 twd1 npc s 0 npc s 1 npc s 2 npc s3 mi s o mo s s pck tclk[ 3 :5] tioa[0:2] tiob[0:2] tioa[ 3 :5] tiob[ 3 :5] pdc pdc pdc pdc pdc pwm in-circ u it em u l a tor pdc jtag & s eri a l wire pwm[0: 3 ] adtrg advref dac0 datrg 10- b it adc 10- b it dac pioc s m vddio pll rxd0 txd0 s ck0 rt s 0 ct s 0 rxd1 txd1 s ck1 rt s 1 ct s 1 u s art0 uart1 uart0 u s art1 cortex-m 3 proce ss or fm a x 4 8 mhz 24- b it s y s tick co u nter rom 16 kbyte s s ram 24 kbyte s 16 kbyte s 8 kbyte s fla s h 256 kbyte s 12 8 kbyte s 64 kbyte s vddcore wdt peripher a l bridge urxd0 utxd0 urxd1 utxd1 timer co u nter a timer co u nter b s pi twi0 twi1 n v i c volt a ge reg u l a tor tc[ 3 ..5] ad[0..15] 3 - l a yer ahb b us m a trix fm a x 4 8 mhz
5 11011bs?atarm?22-feb-12 sam3n summary figure 2-2. sam3n 64-pin version block diagram tc[ 3 ..5] ad[0..9] 3 - l a yer ahb b us m a trix fm a x 4 8 mhz t s t pck0-pck2 s y s tem controller xin nr s t pmc xout o s c 3 2k xin 3 2 xout 3 2 s upc r s tc o s c 3 -20 mhz pioa piob por rtc rtt rc 3 2k rc o s c 12/ 8 /4 mhz era s e tdi tdo/trace s wo tm s / s wdio tck/ s wclk jtag s el i/d s vddi n vddout tc[0..2] tclk[0:2] twck0 twd0 twck1 twd1 npc s 0 npc s 1 npc s 2 npc s3 mi s o mo s s pck tioa[0:2] tiob[0:2] pdc pdc pdc pdc pdc pwm in-circ u it em u l a tor pdc jtag & s eri a l wire pwm[0: 3 ] adtrg advref dac0 datrg 10- b it adc 10- b it dac s m vddio pll rxd0 txd0 s ck0 rt s 0 ct s 0 rxd1 txd1 s ck1 rt s 1 ct s 1 u s art0 uart1 uart0 u s art1 cortex-m 3 proce ss or fm a x 4 8 mhz 24- b it s y s tick co u nter rom 16 kbyte s s ram 24 kbyte s 16 kbyte s 8 kbyte s fla s h 256 kbyte s 12 8 kbyte s 64 kbyte s vddcore wdt peripher a l bridge urxd0 utxd0 urxd1 utxd1 timer co u nter a timer co u nter b s pi twi0 twi1 n v i c volt a ge reg u l a tor 3 -l a yer ahb b us m a trix fm a x 4 8 mhz
6 11011bs?atarm?22-feb-12 sam3n summary figure 2-3. sam3n 48-pin version block diagramz tc[ 3 ..5] ad[0..7] 3 - l a yer ahb b us m a trix fm a x 4 8 mhz t s t pck0-pck2 s y s tem controller xin nr s t pmc xout o s c 3 2k xin 3 2 xout 3 2 s upc r s tc o s c 3 -20 mhz pioa piob por rtc rtt rc 3 2k rc o s c 12/ 8 /4 mhz era s e tdi tdo/trace s wo tm s / s wdio tck/ s wclk jtag s el i/d s vddi n vddout tc[0..1] tclk[0..1] twck0 twd0 twck1 twd1 npc s 0 npc s 1 npc s 2 npc s3 mi s o mo s s pck tioa[0..1] tiob[0..1] pdc pdc pdc pdc pwm in-circ u it em u l a tor pdc jtag & s eri a l wire pwm[0: 3 ] adtrg advref 10- b it adc s m vddio pll rxd0 txd0 s ck0 rt s 0 ct s 0 u s art0 uart1 uart0 cortex-m 3 proce ss or fm a x 4 8 mhz 3 -l a yer ahb b us m a trix fm a x 4 8 mhz 24- b it s y s tick co u nter rom 16 kbyte s s ram 24 kbyte s 16 kbyte s 8 kbyte s 4 kbyte s fla s h 256 kbyte s 12 8 kbyte s 64 kbyte s 3 2 kbyte s 16 kbyte s vddcore wdt peripher a l bridge urxd0 utxd0 urxd1 utxd1 timer co u nter a timer co u nter b s pi twi0 twi1 n v i c volt a ge reg u l a tor
7 11011bs?atarm?22-feb-12 sam3n summary 3. signal description table 3-1 gives details on the signal name classified by peripheral. table 3-1. signal description list signal name function type active level voltage reference comments power supplies vddio peripherals i/o lines power supply power 1.62v to 3.6v vddin voltage regulator, adc and dac power supply power 1.8v to 3.6v (3) vddout voltage regulator output power 1.8v output vddpll oscillator and pll power supply power 1.65 v to 1.95v vddcore power the core, the embedded memories and the peripherals power 1.65v to 1.95v connected externally to vddout gnd ground ground clocks, oscillators and plls xin main oscillator input input vddio reset state: - pio input - internal pull-up disabled - schmitt trigger enabled (1) xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output pck0 - pck2 programmable clock output output reset state: - pio input - internal pull-up enabled - schmitt trigger enabled (1) ice and jtag tck/swclk test clock/serial wire clock input vddio reset state: - swj-dp mode - internal pull-up disabled - schmitt trigger enabled (1) tdi test data in input tdo/traceswo test data out/trace asynchronous data out output tms/swdio test mode select /serial wire input/output input / i/o jtagsel jtag selection input high permanent internal pull-down
8 11011bs?atarm?22-feb-12 sam3n summary flash memory erase flash and nvm configuration bits erase command input high vddio reset state: - erase input - internal pull-down enabled - schmitt trigger enabled (1) reset/test nrst microcontroller reset i/o low vddio permanent internal pull-up tst test mode select input vddio permanent internal pull-down universal asynchronous receiver transceiver - uartx urxdx uart receive data input utxdx uart transmit data output pio controller - pioa - piob - pioc pa0 - pa31 parallel io controller a i/o vddio reset state: - pio or system ios (2) - internal pull-up enabled - schmitt trigger enabled (1) pb0 - pb14 parallel io controller b i/o pc0 - pc31 parallel io controller c i/o universal synchronous asynchronous receiver transmitter usartx sckx usartx serial clock i/o txdx usartx transmit data i/o rxdx usartx receive data input rtsx usartx request to send output ctsx usartx clear to send input timer/counter - tc tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o pulse width modulation controller- pwmc pwmx pwm waveform output for channel x output table 3-1. signal description list (continued) signal name function type active level voltage reference comments
9 11011bs?atarm?22-feb-12 sam3n summary notes: 1. schmitt triggers can be disabled through pio registers. 2. some pio lines are shared with system ios. 3. see section 5.3 ?typical powering schematics? for restriction on voltage range of analog cells. serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o spck spi serial clock i/o spi_npcs0 spi peripheral chip select 0 i/o low spi_npcs1 - spi_npcs3 spi peripheral chip select output low two-wire interface- twix twdx twix two-wire serial data i/o twckx twix two-wire serial clock i/o analog advref adc and dac reference analog 10-bit analog-to-digital converter - adc ad0 - ad15 analog inputs analog adtrg adc trigger input vddio digital-to-analo g converter controller- dacc dac0 dacc channel analog output analog datrg dacc trigger input vddio fast flash programming interface pgmen0-pgmen2 programming enabling input vddio pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low table 3-1. signal description list (continued) signal name function type active level voltage reference comments
10 11011bs?atarm?22-feb-12 sam3n summary 4. package and pinout sam3n4/2/1/0/00 series is pin-to-pin compatible with sam3s products. furthermore sam3n4/2/1/0/00 devices have new functionalities referenced in italic in table 4-1 , table 4-3 and table 4-4 . 4.1 sam3n4/2/1/0/00c package and pinout 4.1.1 100-lead lqfp package outline figure 4-1. orientation of the 100-lead lqfp package 4.1.2 100-ball tfbga package outline the 100-ball tfbga package has a 0.8 mm ball pitch and respects green standards. its dimensions are 9 x 9 x 1.1 mm. figure 4-2. orientation of the 100-ball tfbga package 125 26 50 51 75 76 100 1 3 4 5 6 7 8 9 10 2 abcdefghj k top view ball a1
11 11011bs?atarm?22-feb-12 sam3n summary 4.1.3 100-lead lqfp pinout table 4-1. 100-lead lqfp sam3n4/2/1/0/00c pinout 1 advref 26 gnd 51 tdi/pb4 76 tdo/traceswo/pb5 2 gnd 27 vddio 52 pa6/pgmnoe 77 jtagsel 3 pb0/ad4 28 pa16/pgmd4 53 pa5/pgmrdy 78 pc18 4 pc29/ad13 29 pc7 54 pc28 79 tms/swdio/pb6 5 pb1/ad5 30 pa15/pgmd3 55 pa4/pgmncmd 80 pc19 6 pc30/ad14 31 pa14/pgmd2 56 vddcore 81 pa31 7 pb2/ad6 32 pc6 57 pa27 82 pc20 8 pc31/ad15 33 pa13/pgmd1 58 pc8 83 tck/swclk/pb7 9 pb3/ad7 34 pa24 59 pa28 84 pc21 10 vddin 35 pc5 60 nrst 85 vddcore 11 vddout 36 vddcore 61 tst 86 pc22 12 pa17/pgmd5/ad0 37 pc4 62 pc9 87 erase/pb12 13 pc26 38 pa25 63 pa29 88 pb10 14 pa18/pgmd6/ad1 39 pa26 64 pa30 89 pb11 15 pa21/ad8 40 pc3 65 pc10 90 pc23 16 vddcore 41 pa12/pgmd0 66 pa3 91 vddio 17 pc27 42 pa11/pgmm3 67 pa2/pgmen2 92 pc24 18 pa19/pgmd7/ad2 43 pc2 68 pc11 93 pb13/dac0 19 pc15/ad11 44 pa10/pgmm2 69 vddio 94 pc25 20 pa22/ad9 45 gnd 70 gnd 95 gnd 21 pc13/ad10 46 pa9/pgmm1 71 pc14 96 pb8/xout 22 pa23 47 pc1 72 pa1/pgmen1 97 pb9 /pgmck/xin 23 pc12/ad12 48 pa8/xout32/ pgmm0 73 pc16 98 vddio 24 pa20/ad3 49 pa7/xin32/ pgmnvalid 74 pa0/pgmen0 99 pb14 25 pc0 50 vddio 75 pc17 100 vddpll
12 11011bs?atarm?22-feb-12 sam3n summary 4.1.4 100-ball tfbga pinout table 4-2. 100-ball tfbga sam3n4/2/1/0/00c pinout a1 pb1 c6 pb7 f1 pa18 h6 pc4 a2 pc29 c7 pc16 f2 pc26 h7 pa11 a3 vddio c8 pa1 f3 vddout h8 pc1 a4 pb9 c9 pc17 f4 gnd h9 pa6 a5 pb8 c10 pa0 f5 vddio h10 pb4 a6 pb13 d1 pb3 f6 pa27 j1 pc15 a7 pb11 d2 pb0 f7 pc8 j2 pc0 a8 pb10 d3 pc24 f8 pa28 j3 pa16 a9 pb6 d4 pc22 f9 tst j4 pc6 a10 jtagsel d5 gnd f10 pc9 j5 pa24 b1 pc30 d6 gnd g1 pa21 j6 pa25 b2 advref d7 vddcore g2 pc27 j7 pa10 b3 gndana d8 pa2 g3 pa15 j8 gnd b4 pb14 d9 pc11 g4 vddcore j9 vddcore b5 pc21 d10 pc14 g5 vddcore j10 vddio b6 pc20 e1 pa17 g6 pa26 k1 pa22 b7 pa31 e2 pc31 g7 pa12 k2 pc13 b8 pc19 e3 vddin g8 pc28 k3 pc12 b9 pc18 e4 gnd g9 pa4 k4 pa20 b10 pb5 e5 gnd g10 pa5 k5 pc5 c1 pb2 e6 nrst h1 pa19 k6 pc3 c2 vddpll e7 pa29 h2 pa23 k7 pc2 c3 pc25 e8 pa30 h3 pc7 k8 pa9 c4 pc23 e9 pc10 h4 pa14 k9 pa8 c5 pb12 e10 pa3 h5 pa13 k10 pa7
13 11011bs?atarm?22-feb-12 sam3n summary 4.2 sam3n4/2/1/0/00b package and pinout figure 4-3. orientation of the 64-pad qfn package figure 4-4. orientation of the 64-lead lqfp package 1 16 17 3 2 33 4 8 49 64 top view 33 49 4 8 3 2 17 16 1 64
14 11011bs?atarm?22-feb-12 sam3n summary 4.2.1 64-lead lqfp and qfn pinout 64-pin version sam3n devices are pin-to-pin compatible with sam3s products. furthermore, sam3n products have new functionalities shown in italic in table 4-3 . note: the bottom pad of the qfn pac kage must be connected to ground. table 4-3. 64-pin sam3n4/2/1/0/00b pinout 1 advref 17 gnd 33 tdi/pb4 49 tdo/traceswo/pb5 2 gnd 18 vddio 34 pa6/pgmnoe 50 jtagsel 3 pb0/ad4 19 pa16/pgmd4 35 pa5/pgmrdy 51 tms/swdio/pb6 4 pb1ad5 20 pa15/pgmd3 36 pa4/pgmncmd 52 pa31 5 pb2/ad6 21 pa14/pgmd2 37 pa27/pgmd15 53 tck/swclk/pb7 6 pb3/ad7 22 pa13/pgmd1 38 pa28 54 vddcore 7 vddin 23 pa24/pgmd12 39 nrst 55 erase/pb12 8 vddout 24 vddcore 40 tst 56 pb10 9 pa17/pgmd5/ad0 25 pa25/pgmd13 41 pa29 57 pb11 10 pa18/pgmd6/ad1 26 pa26/pgmd14 42 pa30 58 vddio 11 pa21/pgmd9/ad8 27 pa12/pgmd0 43 pa3 59 pb13/dac0 12 vddcore 28 pa11/pgmm3 44 pa2/pgmen2 60 gnd 13 pa19/pgmd7/ad2 29 pa10/pgmm2 45 vddio 61 xout/pb8 14 pa22/pgmd10/ad9 30 pa9/pgmm1 46 gnd 62 xin/pgmck/pb9 15 pa23/pgmd11 31 pa8/xout32/pgmm 0 47 pa1/pgmen1 63 pb14 16 pa20/pgmd8/ad3 32 pa7/xin32/xout32/ pgmnvalid 48 pa0/pgmen0 64 vddpll
15 11011bs?atarm?22-feb-12 sam3n summary 4.3 sam3n4/2/1/0/00a package and pinout figure 4-5. orientation of the 48-pad qfn package figure 4-6. orientation of the 48-lead lqfp package 1 12 1 3 24 25 3 6 3 7 4 8 top view 25 3 7 3 6 24 1 3 12 1 4 8
16 11011bs?atarm?22-feb-12 sam3n summary 4.3.1 48-lead lqfp and qfn pinout note: the bottom pad of the qfn pac kage must be connected to ground. table 4-4. 48-pin sam3n4/2/1/0/00a pinout 1 advref 13 vddio 25 tdi/pb4 37 tdo/traceswo/ pb5 2 gnd 14 pa16/pgmd4 26 pa6/pgmnoe 38 jtagsel 3 pb0/ad4 15 pa15/pgmd3 27 pa5/pgmrdy 39 tms/swdio/pb6 4 pb1/ad5 16 pa14/pgmd2 28 pa4/pgmncmd 40 tck/swclk/pb7 5 pb2/ad6 17 pa13/pgmd1 29 nrst 41 vddcore 6 pb3/ad7 18 vddcore 30 tst 42 erase/pb12 7 vddin 19 pa12/pgmd0 31 pa3 43 pb10 8 vddout 20 pa11/pgmm3 32 pa2/pgmen2 44 pb11 9 pa17/pgmd5/ad0 21 pa10/pgmm2 33 vddio 45 xout/pb8 10 pa18/pgmd6/ad1 22 pa9/pgmm1 34 gnd 46 xin/p/pb9/gmck 11 pa19/pgmd7/ad2 23 pa8/xout32/pg mm0 35 pa1/pgmen1 47 vddio 12 pa20/ad3 24 pa7/xin32/pgmn valid 36 pa0/pgmen0 48 vddpll
17 11011bs?atarm?22-feb-12 sam3n summary 5. power considerations 5.1 power supplies the sam3n product has several types of power supply pins: ? vddcore pins: power the core, including the processor, the embedded memories and the peripherals. voltage ranges from 1.62v and 1.95v. ? vddio pins: power the peripherals i/o lines, backup part, 32 khz crystal oscillator and oscillator pads. voltage r anges from 1.62v and 3.6v ? vddin pin: voltage regulator, adc and dac power supply. voltage ranges from 1.8v to 3.6v for the voltage regulator ? vddpll pin: powers the pll, the fast rc a nd the 3 to 20 mhz oscillators. voltage ranges from 1.62v and 1.95v. 5.2 voltage regulator the sam3n embeds a voltage regulator that is managed by the supply controller. this internal regulator is intended to supply the internal core of sam3n. it features two different operating modes: ? in normal mode, the voltage regulator consumes less than 700 a static current and draws 60 ma of output current. internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. in wait mode quiescent current is only 7 a. ? in backup mode, the voltage regulator consumes less than 1 a while its output (vddout) is driven internally to gnd. the default output voltage is 1.80v and the start-up time to reach normal mode is less than100 s. for adequate input and output power supply decoupling/bypassing, refer to the voltage regula- tor section in the electrical characteristics section of the datasheet. 5.3 typical powe ring schematics the sam3n supports a 1.62v-3.6v single supply mode. the internal regulator input connected to the source and its output feeds vddcore. figure 5-1 shows the power schematics. as vddin powers the voltage regulator and the adc/dac, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the supc (note that it is dif- ferent from backup mode).
18 11011bs?atarm?22-feb-12 sam3n summary figure 5-1. single supply figure 5-2. core externally supplied note: restrictions with main supply < 3v, adc and dac are not usable. with main supply >= 3v, all peripherals are usable. figure 5-3 below provides an example of the powe ring scheme when using a backup battery. since the pio state is preserved when in backup mode, any free pio line can be used to switch off the external regulator by driving the pio lin e at low level (pio is input, pull-up enabled after backup reset). external wake-up of the system can be from a push button or any signal. see section 5.6 ?wake-up sources? for further details.tfbga main supply (1.8v-3.6v) adc, dac i/os. vddin voltage regulator vddout vddcore vddio vddpll main supply (1.62v-3.6v) can be the same supply vddcore supply (1.62v-1.95v) adc, dac supply (3v-3.6v) adc, dac vddin voltage regulator vddout vddcore vddio vddpll i/os.
19 11011bs?atarm?22-feb-12 sam3n summary figure 5-3. core externally supplied (backup battery) 5.4 active mode active mode is the normal runn ing mode with the core clock runn ing from the fast rc oscillator, the main crystal oscillator or the pll. the power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 low power modes the various low-power modes of the sam3n are described below: 5.5.1 backup mode the purpose of backup mode is to achieve the lo west power consumption possible in a system that is performing periodic wakeups to carry out tasks but not requiring fast startup time (<0.1ms). total current consumption is 3 a typical. the supply controller, zero-power power-on reset, rtt, rtc, backup registers and 32 khz oscillator (rc or crystal oscillator selected by so ftware in the supply cont roller) are running. the regulator and the core supply are off. backup mode is based on the cortex-m3 deep sleep mode with the voltage regulator disabled. the sam3n can be awakened from this mode thro ugh wup0-15 pins, the supply monitor (sm), the rtt or rtc wake-up event. backup mode is enter ed by using wfe instructions with the sleepdeep bit in the system con- trol register of the cortex-m3 set to 1. (see the power management description in the arm cortex m3 processor section of the product datasheet). exit from backup mode happens if one of the following enable wake-up events occurs: ? wkupen0-15 pins (level transition, configurable debouncing) adc, dac i/os. vddin voltage regulator 3.3v ldo backup battery + - on/off in out vddout main supply vddcore adc, dac supply (3v-3.6v) vddio vddpll piox (output) wakeupx external wakeup signal note: the two diodes provide a ?switchover circuit? (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode.
20 11011bs?atarm?22-feb-12 sam3n summary ? supply monitor alarm ?rtc alarm ? rtt alarm 5.5.2 wait mode the purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup ti me of less than 10 s. current consumption in wait mode is typically 15 a (total current consum ption) if the internal voltage regulator is used or 8 a if an external regulator is used. in this mode, the clocks of the core, peripherals and memories are stopped. however, the core, peripherals and memories power supplies are still powered. from this mode, a fast start up is available. this mode is entered via wait for event (wfe) instructions with lpm = 1 (low power mode bit in pmc_fsmr). the cortex-m3 is able to handle exter nal or internal events in order to wake up the core (wfe). by configuring the wup0-15 exter nal lines as fast startup wake-up pins (refer to section 5.7 ?fast start-up? ). rtc or rtt alarm wake-up events can be used to wake up the cpu (exit from wfe). entering wait mode: ? select the 4/8/12 mhz fast rc oscillator as main clock ? set the lpm bit in the pmc fast startup mode register (pmc_fsmr) ? execute the wait-for-event (wfe) instruction of the processor note: internal main cloc k resynchronization cycles are necessa ry between the writing of moscrcen bit and the effective entry in wait mode. depending on the user app lication, waiting for moscrcen bit to be cleared is recommended to en sure that the core will not execute undesired instructions. 5.5.3 sleep mode the purpose of sleep mode is to optimize power consumption of the device versus response time. in this mode, only the core clock is stopped. the peripheral clocks can be enabled. the current consumption in this mode is application dependent. this mode is entered via wait for interrupt (wfi) or wait for event (wfe) instructions with lpm = 0 in pmc_fsmr. the processor can be woke up from an interrupt if wfi instruction of the cortex m3 is used, or from an event if the wfe instruction is used to enter this mode.
21 11011bs?atarm?22-feb-12 sam3n summary 5.5.4 low power mode summary table the modes detailed above are the main low power modes. each part can be set to on or off sep- arately and wake up sources can be individually configured. table 5-1 below shows a summary of the configurations of the low power modes. notes: 1. when considering wake-up time, the time required to start the pll is not taken into accoun t. once started, the device w orks with the 4/8/12 mhz fast rc oscilla tor. the user has to add the pll start-up time if it is nee ded in the system . the wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. the external loads on pios are not taken into account in the calculation. 3. supply monitor current consumption is not included. 4. total current consumption. 5. 5 a on vddcore, 15 a for total current consumption (using internal voltage regulator), 8 a for total current consumption (without using internal voltage regulator). 6. depends on mck frequency. 7. in this mode the core is supplied and not clocked but some peripherals can be clocked. table 5-1. low power mode conf iguration summary mode supc, 32 khz oscillator rtc rtt backup registers, por (backup region) regulator core memory peripherals mode entry potential wake up sources core at wake up pio state while in low power mode pio state at wake up consumption (2) (3) wake up time (1) backup mode on off off (not powered) wfe +sleepdeep bit = 1 wup0-15 pins bod alarm rtc alarm rtt alarm reset previous state saved pioa & piob & pioc inputs with pull ups 3 a typ (4) < 0.1 ms wait mode on on powered (not clocked) wfe +sleepdeep bit = 0 +lpm bit = 1 any event from: fast startup through wup0-15 pins rtc alarm rtt alarm clocked back previous state saved unchanged 5 a/15 a (5) < 10 s sleep mode on on powered (7) (not clocked) wfe or wfi +sleepdeep bit = 0 +lpm bit = 0 entry mode = wfi interrupt only; entry mode = wfe any enabled interrupt and/or any event from: fast start-up through wup0-15 pins rtc alarm rtt alarm clocked back previous state saved unchanged (6) (6)
22 11011bs?atarm?22-feb-12 sam3n summary 5.6 wake-up sources the wake-up events allow the device to exit backup mode. when a wake-up event is detected, the supply controller performs a sequence which aut omatically reenables the core power sup- ply and the sram power supply, if they are not already enabled. figure 5-4. wake-up source wkup15 wkupen15 wkupt15 wkupen1 wkupen0 debouncer slck wkupdbc wkups rtcen rtc_alarm boden brown_out core supply restart wkupis0 wkupis1 wkupis15 falling/rising edge detector wkupt0 falling/rising edge detector wkupt1 falling/rising edge detector wkup0 wkup1 rtten rtt_alarm
23 11011bs?atarm?22-feb-12 sam3n summary 5.7 fast start-up the sam3n allows the processor to restart in a few microseconds while the processor is in wait mode. a fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (wkup0 to 15 + sm + rtc + rtt). the fast restart circuitry, as shown in figure 5-5 , is fully asynchronous and provides a fast start- up signal to the power management controller. as soon as the fast start-up signal is asserted, the pmc automatically restarts the embedded 4 mhz fast rc oscillator, switches the master clock on this 4 mhz clock and reenables the processor clock. figure 5-5. fast start-up sources rtcen rtc_alarm rtten rtt_alarm fast_restart wkup15 fstt15 wkup0 fstt0 falling/rising edge detector falling/rising edge detector
24 11011bs?atarm?22-feb-12 sam3n summary 6. input/output lines the sam3n has several kinds of input/output (i/o) lines such as general purpose i/os (gpio) and system i/os. gpios can have alternate functionality due to mu ltiplexing capabilities of the pio controllers. the same pio line can be used whether in io mode or by the multiplexed peripheral. system i/os include pins such as test pins, oscillators , erase or analog inputs. 6.1 general purpose i/o lines gpio lines are managed by pio controllers. all i/os have several input or output modes such as pull-up or pull-down, input schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. programming of these modes is performed independently for each i/o line through the pio controller user interface. for more details, refer to the product pio control- ler section. the input output buffers of the pio lines are supplied through vddio power supply rail. the sam3n embeds high speed pads able to h andle up to 45 mhz for spi clock lines and 35 mhz on other lines. see ac characteristics section in the electrical characteristics section of the datasheet for more details. typical pull-up and pull-down value is 100 k for all i/os. each i/o line also embeds an odt (on-die termination), (see figure 6-1 ). it consists of an internal series resistor termination scheme for impedance matching between the driver output (sam3n) and the pcb trace impedance preventing si gnal reflection. the series resistor helps to reduce i/o switching current (di/dt) thereby reduc ing in turn, emi. it also decreases overshoot and undershoot (ringing) due to inductance of in terconnect between devices or between boards. in conclusion odt helps dimi nish signal integrity issues. figure 6-1. on-die termination 6.2 system i/o lines system i/o lines are pins used by oscillators, test mode, reset and jtag to name but a few. described below are the sam3n system i/o lines sh ared with pio lines: these pins are software configurable as general purpose i/o or system pins. at startup the default function of these pins is always used. pcb tr a ce z0 ~ 50 ohm s receiver s am 3 driver with rodt zo u t ~ 10 ohm s z0 ~ zo u t + rodt odt 3 6 ohm s ty p.
25 11011bs?atarm?22-feb-12 sam3n summary notes: 1. if pb12 is used as pio input in user applications, a low level must be ensured at start up to prevent flash erase before the user application sets pb12 into pio mode. 2. in the product datasheet refer to: slow clock generator of the supply controller section. 3. in the product datasheet refer to: 3 to 20 mhz crystal oscillator information in the pmc section. 6.2.1 serial wire jtag debug port (swj-dp) pins the swj-dp pins are tck/swclk, tms/sw dio, tdo/swo, tdi and commonly provided on a standard 20-pin jtag connector defined by arm. for more details about voltage reference and reset state, refer to table 3-1 on page 7 . at startup, swj-dp pins are configured in swj-dp mode to allow connection with debugging probe. please refer to the debug and test section of the product datasheet. swj-dp pins can be used as standard i/os to provide users more general input/output pins when the debug port is not needed in the end application. mode selection between swj-dp mode (system io mode) and general io mode is performed through the ahb matrix special function registers (matrix_sfr). configuration of the pad for pull-up, triggers, debouncing and glitch filters is possib le regardless of the mode. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. it integrates a permanent pull-down resistor of about 15 k to gnd, so that it can be left uncon- nected for normal operations. by default, the jtag debug port is active. if the debugger host wants to switch to the serial wire debug port, it must provide a dedicated jtag sequence on tms/swdio and tck/swclk which disables the jtag-dp and enables the sw-dp. when the serial wire debug port is active, tdo/traceswo can be used for trace. the asynchronous trace output (traceswo) is multiplexed with tdo. so the asynchronous trace can only be used with sw-dp, not jtag-dp. for more information about sw-dp and jtag-dp switching, please refer to the debug and test section. table 6-1. system i/o configuration pin list. system_io bit number default function after reset other function constraints for normal start configuration 12 erase pb12 low level at startup (1) in matrix user interface registers (refer to the system i/o configuration register in the bus matrix section of the product datasheet.) 7 tck/swclk pb7 - 6 tms/swdio pb6 - 5 tdo/traceswo pb5 - 4 tdi pb4 - - pa7 xin32 - see footnote (2) below - pa8 xout32 - - pb9 xin - see footnote (3) below - pb8 xout -
26 11011bs?atarm?22-feb-12 sam3n summary 6.3 test pin the tst pin is used for jtag boundary scan manufacturing test or fast flash programming mode of the sam3n series. the tst pin integrates a permanent pull-down resistor of about 15 k to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, see the fast flash programming interface (ffpi) section. for more on the manufacturing and test mode, refer to the ?debug and test? section of the product datasheet. 6.4 nrst pin the nrst pin is bidirectional. it is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. it will reset the core and the peripherals except the backup region (rtc, rtt and supply controller). there is no constraint on the length of the reset pulse and the reset con- troller can guarantee a minimum pulse length. the nrst pin integrates a permanent pull-up resistor to vddio of about 100 k . by default, the nrst pin is configured as an input. 6.5 erase pin the erase pin is used to reinitialize the flash content (and some of its nvm bits) to an erased state (all bits read as logic level 1). it integrates a pull-down resistor of about 100 k to gnd, so that it can be left unconnected for normal operations. this pin is debounced by sclk to improve the glitch tolerance. when the erase pin is tied high during less than 100 ms, it is not taken into account. the pin must be tied high during more than 220 ms to perform a flash erase operation. the erase pin is a system i/o pin and can be used as a standard i/o. at startup, the erase pin is not configured as a pio pin. if the erase pin is used as a standa rd i/o, startup level of this pin must be low to prevent unwanted erasing. please refer to section 11.2 ?peripheral sig- nals multiplexing on i/o lines? on page 42 . also, if the erase pin is used as a standard i/o output, asserting the pin to low does not erase the flash.
27 11011bs?atarm?22-feb-12 sam3n summary 7. processor and architecture 7.1 arm cortex-m3 processor ? version 2.0 ? thumb-2 (isa) subset consisting of all base thumb-2 instructions, 16-bit and 32-bit. ? harvard processor architecture enabling simultaneous instruction fetch with data load/store. ? three-stage pipeline. ? single cycle 32-bit multiply. ? hardware divide. ? thumb and debug states. ? handler and thread modes. ? low latency isr entry and exit. 7.2 apb/ahb bridge the sam3n4/2/1/0/00 product embeds one peripheral bridge: the peripherals of the bridge are clocked by mck. 7.3 matrix masters the bus matrix of the sam3n product manages 3 masters, which means th at each master can perform an access concurrently with others, to an available slave. each master has its own decoder, which is defined specifically for each master. in order to sim- plify the addressing, all the masters have the same decodings. 7.4 matrix slaves the bus matrix of the sam3n product manages 4 slaves. each slave has its own arbiter, allow- ing a different arbitration per slave. table 7-1. list of bus matrix masters master 0 cortex-m3 instruction/data master 1 cortex-m3 system master 2 peripheral dma controller (pdc) table 7-2. list of bus matrix slaves slave 0 internal sram slave 1 internal rom slave 2 internal flash slave 3 peripheral bridge
28 11011bs?atarm?22-feb-12 sam3n summary 7.5 master to slave access all the masters can normally access all the slaves. however, some paths do not make sense, for example allowing access from the cortex-m3 s bus to the internal rom. thus, these paths are forbidden or simply not wired, and shown as ?-? in table 7-3 . 7.6 peripheral dma controller ? handles data transfer between peripherals and memories ? low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory ? next pointer management for reducing interrupt latency requirement the peripheral dma controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): table 7-3. sam3n master to slave access masters 0 1 2 slaves cortex-m3 i/d bus cortex-m3 s bus pdc 0 internal sram - x x 1 internal rom x - x 2 internal flash x - - 3 peripheral bridge - x x table 7-4. peripheral dma controller instance name channel t/r 100 & 64 pins 48 pins twi0 transmit x x uart0 transmit x x usart0 transmit x x dac transmit x n/a spi transmit x x twi0 receive x x uart0 receive x x usart0 receive x x adc receive x x spi receive x x
29 11011bs?atarm?22-feb-12 sam3n summary 7.7 debug and test features ? debug access to all memory and registers in the system, including cortex-m3 register bank when the core is running, halted, or held in reset. ? serial wire debug port (sw-dp) and serial wire jtag debug port (swj-dp) debug access ? flash patch and breakpoint (fpb) unit for implementing breakpoints and code patches ? data watchpoint and trace (dwt) unit for implementing watchpoints, data tracing, and system profiling ? instrumentation trace macrocell (itm) for support of printf style debugging ? ieee1149.1 jtag boundary-can on all digital pins
30 11011bs?atarm?22-feb-12 sam3n summary 8. product mapping figure 8-1. sam3n4/2/1/0/00 product mapping addre ss memory s p a ce code 0x00000000 s ram 0x20000000 peripher a l s 0x40000000 0x60000000 0xa0000000 s y s tem 0xe0000000 0xffffffff offset id peripher a l block code boot memory 0x00000000 intern a l fl as h intern a l rom 0x00400000 0x00800000 0x00c00000 0x1fffffff peripher a l s 0x40000000 0x40004000 s pi 21 0x40008000 0x4000c000 tc0 tc0 0x40010000 23 tc0 tc1 +0x40 24 tc0 tc2 +0x80 25 tc1 tc 3 0x40014000 26 tc1 tc4 +0x40 27 tc1 tc5 +0x80 28 twi0 19 0x40018000 twi1 20 0x4001c000 pwm 31 0x40020000 14 0x40024000 0x40028000 0x4002c000 adc 29 0x40038000 dacc 30 0x4003c000 0x40040000 0x40044000 0x40048000 s y s tem controller 0x400e0000 0x400e2600 0x40100000 s y s tem controller 0x400e0000 matrix 0x400e0200 pmc 5 0x400e0400 uart0 uart1 8 0x400e0600 chipid 0x400e0740 9 0x400e0800 eefc 6 0x400e0a00 0x400e0c00 11 0x400e0e00 piob pioa 12 0x400e1000 pioc 13 0x400e1200 sysc r s tc 0x400e1400 1 sysc s upc +0x10 sysc rtt +0x30 3 sysc wdt +0x50 4 sysc rtc +0x60 2 sysc gpbr +0x90 0x400e1600 0x4007ffff re s erved re s erved re s erved re s erved re s erved re s erved re s erved re s erved re s erved re s erved u s art0 re s erved 0x40200000 re s erved re s erved 3 2 mbyte s b it ba nd a li as 3 2 mbyte s b it ba nd a li as 0x60000000 re s erved re s erved u s art1 15 re s erved re s erved 0x40400000 0x20100000 0x22000000 0x24000000 undefined 1 mbyte b it ba nd region 1 mbyte b it ba nd region
31 11011bs?atarm?22-feb-12 sam3n summary 9. memories 9.1 embedded memories 9.1.1 internal sram the sam3n4 product embeds a total of 24-kbytes high-speed sram. the sam3n2 product embeds a total of 16-kbytes high-speed sram. the sam3n1 product embeds a total of 8-kbytes high-speed sram. the sram is accessible over system cortex-m3 bus at address 0x2000 0000. the sram is in the bit band region. the bit band alias region is from 0x2200 0000 and 0x23ff ffff. ram size must be configurable by calibration fuses. 9.1.2 internal rom the sam3n product embeds an internal rom, which contains the sam boot assistant (sam-ba), in application programming routines (iap) and fast flash programming interface (ffpi). at any time, the rom is mapped at address 0x0080 0000. 9.1.3 embedded flash 9.1.3.1 flash overview the flash of the sam3n4 (256 kbytes) is organized in one bank of 1024 pages of 256 bytes (single plane). the flash of the sam3n2 (128 kbytes) is organize d in one bank of 512 pages of 256 bytes (sin- gle plane). the flash of the sam3n1 (64 kbytes) is organized in one bank of 256 pages of 256 bytes (sin- gle plane). the flash contains a 128-byte write buffer, accessible through a 32-bit interface. 9.1.3.2 flash power supply the flash is supplied by vddcore. 9.1.3.3 enhanced embedded flash controller the enhanced embedded flash controller (eef c) manages accesses performed by the mas- ters of the system. it enab les reading the flash and writing t he write buffer. it also contains a user interface, mapped on the apb. the enhanced embedded flash controller ensures the interface of the flash block with the 32- bit internal bus. its 128-bit wide memory interface increases performance. the user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. it also manages the programming, erasing, locking and unlocking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the system about the flash organization, thus making the software generic.
32 11011bs?atarm?22-feb-12 sam3n summary 9.1.3.4 flash speed the user needs to set the number of wait states depending on the frequency used. for more details, refer to the ac characteristics sub section in the product electrical character- istics section. 9.1.3.5 lock regions several lock bits used to protect write and er ase operations on lock regions. a lock region is composed of several consecutive pages, and each lock region has its associated lock bit. if a locked-region?s erase or program command occurs, the command is aborted and the eefc triggers an interrupt. the lock bits are software programmable through the eefc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 9.1.3.6 security bit feature the sam3n features a security bit, based on a specific general purpose nvm bit (gpnvm bit 0). when the security is enabled, any access to the flash, either through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. this security bit can only be enabled, through the command ?set general purpose nvm bit 0? of the eefc user interface. disabling the security bit can only be achieved by asserting the erase pin at 1, after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash are permitted. it is important to note that the assertion of the erase pin should always be longer than 200 ms. as the erase pin integrates a permanent pull-down, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd fo r the final application. 9.1.3.7 calibration bits nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the cal- ibration bits. 9.1.3.8 unique identifier each device integrates its own 128-bit unique ident ifier. these bits are factory configured and cannot be changed by the user. the erase pin has no e ffect on the unique identifier. table 9-1. lock bit number product number of lock bits lock region size sam3n4 16 16 kbytes (64 pages) sam3n2 8 16 kbytes (64 pages) sam3n1 4 16 kbytes (64 pages)
33 11011bs?atarm?22-feb-12 sam3n summary 9.1.3.9 fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-handshaked parallel port. it allows gang program- ming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when tst and pa0 and pa1are tied low. 9.1.3.10 sam-ba boot the sam-ba boot is a default boot program which provides an easy way to program in-situ the on-chip flash memory. the sam-ba boot assistant supports serial communication via the uart0. the sam-ba boot provides an interface with sam-ba graphic user interface (gui). the sam-ba boot is in rom and is mapped in flash at address 0x0 when gpnvm bit 1 is set to 0. 9.1.3.11 gpnvm bits the sam3n features three gpnvm bits that can be cleared or set respectively through the com- mands ?clear gpnvm bit? and ?set gp nvm bit? of the eefc user interface. . 9.1.4 boot strategies the system always boots at address 0x0. to ens ure a maximum boot possibilities the memory layout can be changed via gpnvm. a general purpose nvm (gpnvm) bit is used to boot either on the rom (default) or from the flash. the gpnvm bit can be cleared or set respectively through the commands ?clear general-pur- pose nvm bit? and ?set general-purpose nvm bit? of the eefc user interface. setting the gpnvm bit 1 selects the boot from the flash, clearing it selects the boot from the rom. asserting erase clears the gpnvm bit 1 and thus selects the boot from the rom by default. table 9-2. general-purpose non volatile memory bits gpnvmbit[#] function 0 security bit 1 boot mode selection
34 11011bs?atarm?22-feb-12 sam3n summary 10. system controller the system controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... see the system controller block diagram in figure 10-1 on page 35 .
35 11011bs?atarm?22-feb-12 sam3n summary figure 10-1. system controller block diagram s oftw a re controlled volt a ge reg u l a tor adc pioa/b/c m a trix s ram cortex-m 3 fl as h peripher a l s peripher a l bridge zero-power power-on re s et su pply monitor (b a ck u p) rtc em b edded 3 2 khz rc o s cill a tor xt a l 3 2 khz o s cill a tor su pply controller browno u t detector (core) gener a l p u rpo s e b a ck u p regi s ter s re s et controller b a ck u p power su pply core power su pply vr_on vr_mode b od_on b rown_o u t rtc_ a l a rm s lck rtc_nre s et proc_nre s et periph_nre s et ice_nre s et m as ter clock mck s lck core_nre s et m a in clock mainck s lck nr s t f s tt0 - f s tt15 xin 3 2 xout 3 2 o s c 3 2k_xt a l_en o s c 3 2k_ s el s low clock s lck o s c 3 2k_rc_en core_nre s et vddio vddcore vddout advref adx wkup0 - wkup15 b od_core_on lcore_ b rown_o u t rtt rtt_ a l a rm s lck rtt_nre s et xin xout vddio vddin piox dac dac0 pll f s tt0 - f s tt15 a re po ss i b le f as t s t a rt u p s o u rce s , gener a ted b y wkup0-wkup15 pin s , bu t a re not phy s ic a l pin s . em b edded 12/ 8 /4 mhz rc o s cill a tor xt a l o s cill a tor w a tchdog timer power m a n a gement controller
36 11011bs?atarm?22-feb-12 sam3n summary 10.1 system controller and peripherals mapping please refer to figure 8-1, "sam3n4/2/1/0/00 product mapping" on page 30 . all the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 power-on-reset, brownout and supply monitor the sam3n embeds three features to monitor, warn and/or reset the chip: ? power-on-reset on vddio ? brownout detector on vddcore ? supply monitor on vddio 10.2.1 power-on-reset the power-on-reset monitors vddi o. it is always activated and monitors voltage at start up but also during power down. if vddio goes below the threshold voltage, the entire chip is reset. for more information, refer to the electrical characteristics section of the datasheet. 10.2.2 brownout detector on vddcore the brownout detector monitors v ddcore. it is active by default. it can be deactivated by soft- ware through the supply controller (supc_mr). it is especially recommended to disable it during low-power modes such as wait or sleep modes. if vddcore goes below the thresh old voltage, the reset of the co re is asserted. for more infor- mation, refer to the supply controller (supc) and electrical characteristics sections of the datasheet. 10.2.3 supply monitor on vddio the supply monitor monitors vddio. it is inactive by default. it can be activated by software and is fully programmable with 16 steps for the thres hold (between 1.9v to 3.4v). it is controlled by the supply controller (supc). a samp le mode is possible. it allows to divide the supply monitor power consumption by a factor of up to 2048. for more information, refer to the supc and elec- trical characteristics sections of the datasheet. 10.3 reset controller the reset controller is based on a power-on-r eset cell, and a supply monitor on vddcore. the reset controller is capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. the reset controller controls the internal resets of the system a nd the nrst pin input/output. it is capable to shape a reset signal for the exter nal devices, simplifying to a minimum connection of a push-button on the nrst pin to implement a manual reset. the configuration of the reset controller is saved as supplied on vddio. 10.4 supply controller (supc) the supply controller controls the power suppl ies of each section of the processor and the peripherals (via voltage regulator control) the supply controller has its own reset circui try and is clocked by the 32 khz slow clock generator.
37 11011bs?atarm?22-feb-12 sam3n summary the reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. the zero-power power-on reset allows the supply controller to start properly, while the soft- ware-programmable brownout detector allows det ection of either a battery discharge or main voltage loss. the slow clock generator is based on a 32 kh z crystal oscillator and an embedded 32 khz rc oscillator. the slow clock defaul ts to the rc oscillator, but th e software can enable the crystal oscillator and select it as the slow clock source. the supply controller starts up the device by sequentially enabling the internal power switches and the voltage regulator, then it generates the proper reset signals to the core power supply. it also enables to set the system in different low power modes and to wake it up from a wide range of events. 10.5 clock generator the clock generator is made up of: ? one low power 32768hz slow clock oscillator with bypass mode ? one low-power rc oscillator ? one 3-20 mhz crystal or ceramic res onator oscillator, which can be bypassed ? one fast rc oscillator factory programmed, 3 ou tput frequencies can be selected: 4, 8 or 12 mhz. by default 4 mhz is selected. ? one 60 to 130 mhz programmable pll, capable to provide the clock mck to the processor and to the peripherals. the input frequency of pll is from 3.5 to 20 mhz. figure 10-2. clock generator block diagram xin xout main clock mainck slow clock slck xin32 xout32 clock generator xtalsel mainsel power management controller control status pll and divider a plla clock pllack 3-20 mhz main oscillator slow clock oscillator on chip 12/8/4 mhz rc osc on chip 32 khz rc osc
38 11011bs?atarm?22-feb-12 sam3n summary 10.6 power management controller the power management controller provides all the clock signals to the system. it provides: ? the processor clock hclk ? the free running processor clock fclk ? the cortex systick external clock ? the master clock mck, in particular to the matrix and the memory interfaces ? independent peripheral clocks, typically at the frequency of mck ? three programmable clock outputs: pck0, pck1 and pck2 the supply controller selects between the 32 khz rc oscillator or the crystal oscillator. the unused oscillator is disabled automatically so that powe r consumption is optimized. by default, at startup the chip runs out of th e master clock using the fast rc oscillator running at 4 mhz. the user can trim by software the 8 and 12 mhz rc oscillator frequency. figure 10-3. sam3n4/2/1/0/00 power management controller block diagram the systick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms with systick clock at 6 mhz (48 mhz/8) 10.7 watchdog timer ? 16-bit key-protected only-once-programmable counter ? windowed, prevents the processor to be in a dead-lock on the watchdog access mck periph_clk[..] int s lck mainck pre s c a ler /1,/2,/4,..,/64 hck proce ss or clock controller s leep mode m as ter clock controller peripher a l s clock controller on/off s lck mainck pre s c a ler /1,/2,/4,..,/64 progr a mm ab le clock controller pck[..] on/off fclk s y s ttick divider / 8 pllck pllck
39 11011bs?atarm?22-feb-12 sam3n summary 10.8 systick timer ? 24-bit down counter ? self-reload capability ? flexible system timer 10.9 real-time timer ? real-time timer, allowing backup of time with different accuracies ? 32-bit free-running back-up counter ? integrates a 16-bit programmable prescaler running on slow clock ? alarm register capable to generate a wake-up of the system through the shut down controller 10.10 real time clock ? low power consumption ? full asynchronous design ? two hundred year calendar ? programmable periodic interrupt ? alarm and update parallel load ? control of alarm and update time/calendar data in 10.11 general purpose backup registers ? eight 32-bit general-purpose backup registers 10.12 nested vectored interrupt controller ? thirty two maskable external interrupts ? sixteen priority levels ? processor state automatically saved on interrupt entry, and restored on ? dynamic reprioritization of interrupts ? priority grouping ? selection of pre-empting interrupt levels and non pre-empting interrupt levels ? support for tail-chaining and late arrival of interrupts ? back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. ? processor state automatically saved on interrupt entry and restored on interrupt exit, with no instruction overhead
40 11011bs?atarm?22-feb-12 sam3n summary 10.13 chip identification ? chip identifier (chipid) registers permit recognition of the device and its revision. ? jtag id: 0x05b2e03f 10.14 uart ?two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? support for two pdc channels with connection to receiver and transmitter 10.15 pio controllers ? 3 pio controllers, pioa, piob and pioc (100-pin version only) controlling a maximum of 79 i/o lines ? each pio controller controls up to 32 programmable i/o lines ? fully programmable through set/clear registers ? multiplexing of four peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change, rising edge, falling ed ge, low level and level interrupt ? debouncing and glitch filter table 10-1. sam3n chip id register chip name chipid_cidr chipid_exid atsam3n4c (rev a) 0x29540960 0x0 atsam3n2c (rev a) 0x29590760 0x0 atsam3n1c (rev a) 0x29580560 0x0 atsam3n4b (rev a) 0x29440960 0x0 atsam3n2b (rev a) 0x29490760 0x0 atsam3n1b (rev a) 0x29480560 0x0 atsam3n4a (rev a) 0x29340960 0x0 atsam3n2a (rev a) 0x29390760 0x0 atsam3n1a (rev a) 0x29380560 0x0 table 10-2. pio available according to pin count version 48 pin 64 pin 100 pin pioa 21 32 32 piob 13 15 15 pioc --32
41 11011bs?atarm?22-feb-12 sam3n summary ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time ? selection of the drive level ? synchronous output, provides set and clear of several i/o lines in a single write 11. peripherals 11.1 peripheral identifiers table 11-1 defines the peripheral identifiers of the sam3n4/2/1/0/00. a peripheral identifier is required for the control of the peripheral interrupt with the nested vectored interrupt controller and for the control of the peripheral clock with the power management controller. table 11-1. peripheral identifiers instance id instance name nv ic interrupt pmc clock co ntrol instance description 0 supc x supply controller 1 rstc x reset controller 2 rtc x real time clock 3 rtt x real time timer 4 wdt x watchdog timer 5 pmc x power management controller 6 eefc x enhanced flash controller 7 - - reserved 8 uart0 xx uart 0 9 uart1 xx uart 1 10 - -- reserved 11 pioa xx parallel i/o controller a 12 piob xx parallel i/o controller b 13 pioc xx parallel i/o controller c 14 usart0 xx usart 0 15 usart1 xx usart 1 16 - -- reserved 17 - -- reserved 18 - -- reserved 19 twi0 xx two wire interface 0 20 twi1 xx two wire interface 1 21 spi xx serial peripheral interface 22 - -- reserved 23 tc0 xx timer/counter 0 24 tc1 xx timer/counter 1
42 11011bs?atarm?22-feb-12 sam3n summary 11.2 peripheral signals mu ltiplexing on i/o lines the sam3n product features 2 pio controllers ( 48-pin and 64-pin version) or 3 pio controllers (100-pin version), pioa, piob and pioc, that multiplex the i/o lines of the peripheral set. the sam3n 64-pin and 100-pin pio controller controls up to 32 lines (see table 10-2, ?pio available according to pin count,? on page 40 ). each line can be assigned to one of three periph- eral functions: a, b or c. the multiplexing tables in the following paragraphs define how the i/o lines of the peripherals a, b and c are multiplexed on the pio controllers. the column ?com- ments? has been inserted in this table for the user?s own comments; it may be used to track how pins are defined in an application. note that some peripheral functions which are ou tput only, might be duplicated within the tables. 25 tc2 xx timer/counter 2 26 tc3 xx timer/counter 3 27 tc4 xx timer/counter 4 28 tc5 xx timer/counter 5 29 adc xx analog-to-digital converter 30 dacc xx digital-to-analog converter 31 pwm xx pulse width modulation table 11-1. peripheral identifiers (continued) instance id instance name nv ic interrupt pmc clock co ntrol instance description
43 11011bs?atarm?22-feb-12 sam3n summary 11.2.1 pio controller a multiplexing table 11-2. multiplexing on pi o controller a (pioa) i/o line peripheral a peripheral b periphera l c extra function system function comments pa0 pwm0 tioa0 wkup0 high drive pa1 pwm1 tiob0 wkup1 high drive pa2 pwm2 sck0 datrg wkup2 high drive pa 3 t w d 0 n p c s 3 high drive pa4 twck0 tclk0 wkup3 pa5 rxd0 npcs3 wkup4 pa 6 t x d 0 p c k 0 pa 7 rt s 0 p w m 3 x i n 3 2 pa8 cts0 adtrg wkup5 xout32 pa9 urxd0 npcs1 wkup6 pa10 utxd0 npcs2 pa11 npcs0 pwm0 wkup7 pa12 miso pwm1 pa13 mosi pwm2 pa14 spck pwm3 wkup8 pa15 tioa1 wkup14 pa16 tiob1 wkup15 pa17 pck1 ad0 pa18 pck2 ad1 pa19 ad2/wkup9 pa20 ad3/wkup10 pa21 rxd1 pck1 ad8 64/100-pin versions pa22 txd1 npcs3 ad9 64/100-pin versions pa23 sck1 pwm0 64/100-pin versions pa24 rts1 pwm1 64/100-pin versions pa25 cts1 pwm2 64/100-pin versions pa26 tioa2 64/100-pin versions pa27 tiob2 64/100-pin versions pa28 tclk1 64/100-pin versions pa29 tclk2 64/100-pin versions pa30 npcs2 wkup11 64/100-pin versions pa31 npcs1 pck2 64/100-pin versions
44 11011bs?atarm?22-feb-12 sam3n summary 11.2.2 pio controller b multiplexing table 11-3. multiplexing on pi o controller b (piob) i/o line peripheral a peripheral b peripheral c extra function syst em function comments pb0 pwm0 ad4 pb1 pwm1 ad5 pb2 urxd1 npcs2 ad6/wkup12 pb3 utxd1 pck2 ad7 pb4 twd1 pwm2 tdi pb5 twck1 wkup13 tdo/ traceswo pb6 tms/swdio pb7 tck/swclk pb8 xout pb9 xin pb10 pb11 pb12 erase pb13 pck0 dac0 64/100-pin versions pb14 npcs1 pwm3 64/100-pin versions
45 11011bs?atarm?22-feb-12 sam3n summary 11.2.3 pio controller c multiplexing i/o line peripheral a peripheral b periphera l c extra function system function comments pc0 100-pin version pc1 100-pin version pc2 100-pin version pc3 100-pin version pc4 npcs1 100-pin version pc5 100-pin version pc6 100-pin version pc7 npcs2 100-pin version pc8 pwm0 100-pin version pc9 pwm1 100-pin version pc10 pwm2 100-pin version pc11 pwm3 100-pin version pc12 ad12 100-pin version pc13 ad10 100-pin version pc14 pck2 100-pin version pc15 ad11 100-pin version pc16 pck0 100-pin version pc17 pck1 100-pin version pc18 pwm0 100-pin version pc19 pwm1 100-pin version pc20 pwm2 100-pin version pc21 pwm3 100-pin version pc22 pwm0 100-pin version pc23 tioa3 100-pin version pc24 tiob3 100-pin version pc25 tclk3 100-pin version pc26 tioa4 100-pin version pc27 tiob4 100-pin version pc28 tclk4 100-pin version pc29 tioa5 ad13 100-pin version pc30 tiob5 ad14 100-pin version pc31 tclk5 ad15 100-pin version
46 11011bs?atarm?22-feb-12 sam3n summary 12. embedded peripherals overview 12.1 serial peripheral interface (spi) ? supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfers on the same device 12.2 two wire interface (twi) ? master, multi-master and slave mode operation ? compatibility with atmel two-wire interface, serial memory and i 2 c compatible devices ? one, two or three bytes for slave address ? sequential read/write operations ? bit rate: up to 400 kbit/s ? general call supported in slave mode ? connecting to pdc channel capabilities optimizes data transfers in master mode only (for twi0 only) ? one channel for the receiver, one channel for the transmitter ? next buffer support 12.3 universal asynchronous r eceiver transceiver (uart) ?two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes
47 11011bs?atarm?22-feb-12 sam3n summary ? support for two pdc channels with connection to receiver and transmitter (for uart0 only) 12.4 usart ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards (only on usart0) ? nack handling, error counter with repetition and iteration limit ? spi mode ?master or slave ? serial clock programmable phase and polarity ? spi serial clock (sck) frequency up to mck/4 ? irda modulation and demodulation (only on usart0) ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo ? pdc support (for usart0 only) 12.5 timer counter (tc) ? six 16-bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs
48 11011bs?atarm?22-feb-12 sam3n summary ? two multi-purpose input/output signals ? two global registers that act on all three tc channels ? quadrature decoder ? advanced line filtering ? position/revolution/speed ? 2-bit gray up/down counter for stepper motor 12.6 pulse width modulatio n controller (pwm) ? four channels, one 16-bit counter per channel ? common clock generator, providing thirteen different clocks ? one modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channel programming ? independent enable/disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? programmable selection of the output waveform polarity 12.7 10-bit analog-to-digital converter ? up to 16-channel adc ? 10-bit 384 ksamples/sec. or 8-bit 583 ksam ples/sec. successive approximation register adc ? 2 lsb integral non linearity, 1 lsb differential non linearity ? integrated 8-to-1 multiplexer, offering eight independent 3.3v analog inputs ? external voltage reference for better accuracy on low voltage inputs ? individual enable and disable of each channel ? multiple trigger source ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger ? sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 12.8 digital-to-analog converter (dac) ? 1 channel 10-bit dac ? up to 500 ksamples/s conversion rate ? flexible conversion range ? multiple trigger sources ? one pdc channel
49 11011bs?atarm?22-feb-12 sam3n summary 13. package drawings the sam3n series devices are available in lqfp, qfn and tfbga packages. figure 13-1. 100-lead lqfp package drawing note : 1. this drawing is for general information only. refer to jedec drawing ms-026 for additional information.
50 11011bs?atarm?22-feb-12 sam3n summary figure 13-2. 100-ball tfbga package drawing
51 11011bs?atarm?22-feb-12 sam3n summary figure 13-3. 64- and 48-lead lqfp package drawing
52 11011bs?atarm?22-feb-12 sam3n summary table 13-1. 48-lead lqfp package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ?1.60? ?0.063 a1 0.05 ? 0.15 0.002 ? 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 9.00 bsc 0.354 bsc d1 7.00 bsc 0.276 bsc e 9.00 bsc 0.354 bsc e1 7.00 bsc 0.276 bsc r2 0.08 ? 0.20 0.003 ? 0.008 r1 0.08 ? ? 0.003 ? ? q 03.57 03.57 1 0??0?? 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 ? 0.20 0.004 ? 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 ? ? 0.008 ? ? b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d2 5.50 0.217 e2 5.50 0.217 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
53 11011bs?atarm?22-feb-12 sam3n summary table 13-2. 64-lead lqfp package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ?1.60? ?0.063 a1 0.05 ? 0.15 0.002 ? 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 12.00 bsc 0.472 bsc d1 10.00 bsc 0.383 bsc e 12.00 bsc 0.472 bsc e1 10.00 bsc 0.383 bsc r2 0.08 ? 0.20 0.003 ? 0.008 r1 0.08 ? ? 0.003 ? ? q 03.57 03.57 1 0??0?? 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 ? 0.20 0.004 ? 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 ? ? 0.008 ? ? b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d2 7.50 0.285 e2 7.50 0.285 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
54 11011bs?atarm?22-feb-12 sam3n summary figure 13-4. 48-pad qfn package drawing
55 11011bs?atarm?22-feb-12 sam3n summary table 13-3. 48-pad qfn package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ? 090 ? ? 0.035 a1 ? ? 0.050 ? ? 0.002 a2 ? 0.65 0.70 ? 0.026 0.028 a3 0.20 ref 0.008 ref b 0.18 0.20 0.23 0.007 0.008 0.009 d 7.00 bsc 0.276 bsc d2 5.45 5.60 5.75 0.215 0.220 0.226 e 7.00 bsc 0.276 bsc e2 5.45 5.60 5.75 0.215 0.220 0.226 l 0.35 0.40 0.45 0.014 0.016 0.018 e 0.50 bsc 0.020 bsc r 0.09 ? ? 0.004 ? ? tolerances of form and position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002
56 11011bs?atarm?22-feb-12 sam3n summary figure 13-5. 64-pad qfn package drawing
57 11011bs?atarm?22-feb-12 sam3n summary 14. ordering information table 14-1. ordering code mrl flash (kbytes) package package type temperature operating range atsam3n4ca-au a 256 lqfp100 green industrial -40c to 85c atsam3n4ca-cu a 256 tfbga100 green industrial -40c to 85c atsam3n4ba-au a 256 lqfp64 green industrial -40c to 85c atsam3n4ba-mu a 256 qfn64 green industrial -40c to 85c atsam3n4aa-au a 256 lqfp48 green industrial -40c to 85c atsam3n4aa-mu a 256 qfn48 green industrial -40c to 85c atsam3n2ca-au a 128 lqfp100 green industrial -40c to 85c atsam3n2ca-cu a 128 tfbga100 green industrial -40c to 85c atsam3n2ba-au a 128 lqfp64 green industrial -40c to 85c atsam3n2ba-mu a 128 qfn64 green industrial -40c to 85c atsam3n2aa-au a 128 lqfp48 green industrial -40c to 85c atsam3n2aa-mu a 128 qfn48 green industrial -40c to 85c atsam3n1ca-au a 64 lqfp100 green industrial -40c to 85c atsam3n1cb-au b 64 lqfp100 green industrial -40c to 85c atsam3n1ca-cu a 64 tfbga100 green industrial -40c to 85c atsam3n1cb-cu b 64 tfbga100 green industrial -40c to 85c atsam3n1ba-au a 64 lqfp64 green industrial -40c to 85c atsam3n1bb-au b 64 lqfp64 green industrial -40c to 85c atsam3n1ba-mu a 64 qfn 64 green industrial -40c to 85c atsam3n1bb-mu b 64 qfn 64 green industrial -40c to 85c
58 11011bs?atarm?22-feb-12 sam3n summary atsam3n1aa-au a 64 lqfp48 green industrial -40c to 85c atsam3n1ab-au b 64 lqfp48 green industrial -40c to 85c atsam3n1aa-mu a 64 qfn48 green industrial -40c to 85c atsam3n1ab-mu b 64 qfn48 green industrial -40c to 85c atsam3n0ca-au a 32 lqfp100 green industrial -40c to 85c atsam3n0ca-cu a 32 tfbga100 green industrial -40c to 85c atsam3n0ba-au a 32 lqfp64 green industrial -40c to 85c atsam3n0ba-mu a 32 qfn64 green industrial -40c to 85c atsam3n0aa-au a 32 lqfp48 green industrial -40c to 85c atsam3n0aa-mu a 32 qfn48 green industrial -40c to 85c atsam3n00ba-au a 16 lqfp64 green industrial -40c to 85c atsam3n00ba-mu a 16 qfn64 green industrial -40c to 85c ATSAM3N00AA-AU a 16 lqfp48 green industrial -40c to 85c atsam3n00aa-mu a 16 qfn48 green industrial -40c to 85c table 14-1. ordering code mrl flash (kbytes) package package type temperature operating range
59 11011bs?atarm?22-feb-12 sam3n summary revision history doc. rev. 11011bs comments change request ref. overview: all mentions of 100-ball lfbg a changed into 100-ball tfbga section 8. ?product mapping? , heading was ?memories?. changed to ?product mapping? section 4.1.4 ?100-ball tfbga pinout? , whole pinout table updated updated package dimensions in ?features? 8044 7685 7201 7965 doc. rev comments change request ref. 11011as first issue
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